In this phase we will add the Memory Management layer to our toy OS. We will implement demand-paging. Set page size to 8 words, therefore there are 32 frames in our 256 word memory. Each entry in page

In this phase we will add the Memory Management layer to our toy OS. We will implement demand-paging. Set page size to 8 words, therefore there are 32 frames in our 256 word memory. Each entry in page table consists of the frame number, the valid/invalid-bit, and the modify-bit. We will use two page replacement algorithms, FIFO and LRU. When a page-fault occurs, the offending process is placed in the wait queue with the trap completion time set to 27 clock ticks later–same as I/O operations. After a page fault is serviced, that is 27 or more clock ticks have passed, the process is moved to ready queue. Once a page-fault occurs, you may load the new page into memory immediately. This way when page-fault has been serviced (its time is reached or has passed) the page is already in memory.

In addition to the information gathered in Phase II, for each process compute:

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In this phase we will add the Memory Management layer to our toy OS. We will implement demand-paging. Set page size to 8 words, therefore there are 32 frames in our 256 word memory. Each entry in page
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Number of Page-faults and Hit Ratio

Hit Ratio is the percentage of non-page fault memory references.

You will need to add a Translation Look-aside Buffer (TLB) to the Virtual Machine (VM). Without a TLB, and assuming a PTBR, every logical memory reference results in two physical memory references and hence a slower system.

Inclusion of TLB is both more realistic and simplifies the OS! If a memory reference is found in TLB it is handled in the hardware/VM and it takes 4 time units; otherwise, it results in a trap to the OS. Every time a new process takes over the VM, it copies its page table content onto the TLB as part of the context switch process.

All logical addresses in a program are translated at run time (by VM) to physical memory addresses through TLB. This includes pc as well. Every time a program refers to a logical address or VM increments pc, VM first compares the address withlimit to make sure an out of bound reference has not occurred, then it computes its equivalent physical address by mapping it through TLB. If the physical address is not found, because the page that contains it is not in memory (it’s invalid), then a page fault results and VM returns. Of course, all of this happens within the VM.

To support LRU, add 32 registers to the VM–one register per frame. These “frame registers” can be represented by a vector of integers. Each time a frame is accessed, the hardware saves the current time in its corresponding register. OS accesses frame registers to perform the LRU page replacement algorithm.

FIFO doesn’t need these frame registers. The OS maintains its own vector of (software) frame registers, and FIFO is entirely done by the OS without hardware help. When a page is brought into memory, the OS records the current time in its corresponding software frame register. The page-fault handling section of OS consults software frame registers to select the victim page.

Run your OS twice, once with LRU and once with FIFO page replacement algorithm for the same set of programs.

$ os -fifo$ os -lru

This way the merits of the two algorithms can be compared. Use seekp() to replace a page in .o file which serves as the simulated disk. Note that you don’t need to replace a page if its corresponding frame has not been modified.

As far as stack is concerned, it takes up as many pages as necessary in high memory. Memory locations taken up by stack will not be available for paging purposes. If the stack grows too large trying to overwrite an allocated frame, that frame has to move out (and replaced on disk if necessary) before the stack can grow any larger.

We will fix degree of multiprogramming at 5; only 5 PCBs are in either ready queue, wait queue, or CPU at the same time. When the OS starts, it assembles 5 .s files to their corresponding .o files, loads in the first page of each .o file into memory, sets up their page tables, sets up their PCBs in ready queue, and starts executing the first process.

As the processes are executed, more pages are brought in based on the availability of frames and requests of the processes. Only when a process exits, a new process is added to the system to maintain a degree of multiprogramming equal to 5. Note that in this phase we need to add “Page Fault” as a new condition for context switch in addition to the conditions in Phase II. We use bit 10 of status register (SR) in conjunction with bits 5-7 to represent page fault. When bits 5-7 are all zeros and bit 10 is 0, we have a time-slice interrupt. When bits 5-7 are all zeros and bit 10 is 1, we have a page fault interrupt. And in case of a page fault, VM uses bits 11 through 15 to let OS know which page to bring in.

Here is the new configuration of SR:

  Page#    PF    I/O Reg    VM Ret Status    V    L    E    G    C    15:11  10      9:8          7:5  4  3  2  1  0

Add four more .s programs: addVector.s, subVector.s, simple1.s, and simple2.s to the list of programs from Phase II for a total of 10 programs. The input files for the vector programs are addVector.in and subVector.in.

Since the ls command lists files in alphabetical order, the order in which the programs are brought in, as a result of

system(“ls *.s > progs”);

is as follows:

addVector.s fact1.s fact2.s io.s simple1.s simple2.s sub.s subVector.s sum1.s sum2.s

To incrementally develop your OS, first make sure that your program runs correctly for just simple1.s and simple2.s. That is the OS has only the above two programs to run. A quick inspection of theses two programs reveals that each generates only one page fault and 28 frames remain free. This implies there is no need for a page replacement algorithm in this first step. After these two programs run correctly, then try running more programs at the same time.

Demonstrate your program and hand in printouts of your source code and all .out files for each page replacement algorithm. The same grading criteria as Phase I and II holds.

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